So, it seems from another thread that the general consensus is somewhat against clock gating. I'm still somewhat new at the whole FPGA thing, so I was hoping for some input as to:
a) Is this a general rule, or does it only apply to high speed clocks, and if so, what starts to become "high speed"?
b) I'm using a Spartan III and currently using a BUFGCE to gate a 40 MHz clock that is only used externally. Is this poor form, or is it just clock gating through LUTs that's frowned upon?
Any advice is, as always appreciated.
-- Rob