Clock Gating

So, it seems from another thread that the general consensus is somewhat against clock gating. I'm still somewhat new at the whole FPGA thing, so I was hoping for some input as to:

a) Is this a general rule, or does it only apply to high speed clocks, and if so, what starts to become "high speed"?

b) I'm using a Spartan III and currently using a BUFGCE to gate a 40 MHz clock that is only used externally. Is this poor form, or is it just clock gating through LUTs that's frowned upon?

Any advice is, as always appreciated.

-- Rob

Reply to
Rob Gaddi
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-- Mike Treseler

Reply to
Mike Treseler

Clock gating has two bad effects: The output of the gating is unavoidably delayed, so you end up with two flavors of the same basic clock, but with a slight timing difference. Can lead to bad hold-time isseus when your signal crosses between the domains.

But the biggest problem occurs when the gating signal is asynchronous with the clock being gated. Then all hell breakes loose, since it will generate runt pulses and slivers in a totally uncontrolled way. There are clever ways around this (as I described in TechXclusives "Six Easy Pieces" and as implemented in the Virtex-4 clock multiplexer), but most savvy designers consider clock gating a "criminal offense".

Peter Alfke

Reply to
Peter Alfke

When we used clock gating in PALs, GALs and even most CPLDs we could be aware that every path had almost (sub nano second) the same delay. This made things happen that were not possible in a different way with those devices. FPGAs are very different in one point: Delay! Thus you will likely get glitches and runt pulses and even a reroute won't give you a predictable result. You should avoid this. Today you simply have enough speed to double the clock if you want to adapt an old design.

Regards, Thomas

Reply to
Thomas Rudloff

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