Slice Virtex II = Equivalent gates ??

Give up, this is hopeless. The structures are so different, there is no conversion factor. Let me give you the extremes:

The 4-input LUT can be used as either an inverter or a 10-gate XOR structure, or as a 64+-gate 16-bit RAM, or as a 100-gate sixteen bit shift register. The associated fancy flip-flop is worth 7+ gates. And a slice is twice what I listed above, so it's anything from 2 gates to 214 gates. Is that enough leeway? Some people use the geometric mean value of 14... Peter Alfke, Xilinx Applications

Too bad some marketing guys didn't give up this way of counting earlier ;-)

Howdy,

If I had to make a WAG, the marketing department would claim that it isn't their fault: "the customer asked for it!" But the marketing guy that says this doesn't realize that the proper answer isn't a number - it's an explaination as to why any number they provide won't be accurate. Then the customer says "but the other FPGA vendor gave me a number - why can't you?"

Customers are such a pain. :-)

Have fun,

Marc

gates

How about a slightly different question. How many gates (NAND2 equivalent) does it take to implement a slice? Or alteranatively, what's the area of a slice? I'd be interested to know for an older device if you can't give out details of your latest devices.

Cheers, Jon

Since FPGA resources can be used many different ways, there is a 1:100 ratio between the worst and best case FPGA resources to ASIC gates.

If you have HDL code, you can synthesise it for both FPGA and ASIC, and extract some numbers. The ratio you get will be a reasonable estimate for similar designs.

You may find the following helpful, or at least interesting:

=================== Philip Freidin snipped-for-privacy@fpga-faq.org Host for

Why would you want to know? A slice uses a large number of gates, but is laid out very efficiently. This structure is highly specialized and has >20 years of evolution behind it. I think there is nothing to be learned from it, except how to build FPGAs. Peter Alfke