Hi ,
I have a Virtex II Pro FPGA Board and I have a verilog HDL code, I synthesized and generated bit stream to configure the FPGA. Now unable to solve the following questions.
how can I test that code on the board ? I mean how to find verify its functionality . how can I drive the input data to the code? how can I observe the outputs for the given inputs?
Please help me in this regard.
Regards, Kishore