ACTEL design problems

Hi, my ACTEL FPGA design shows significant problems. A bit that is feed in a FIFO will set more than one flipflop. The flipflops a feed by the same clock but it seem that there is a setup/hold problem. Some signals shows glitches (even between flipflops of a FIFO) ???? This is synchonous design! Does anybody know how to fix this problems ? rupert