Tutorial on debug of packet processing in FPGA hardware using Identify

May 12, 2005 1 Replies

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For those of us that build packet processing circuits in FPGA hardware, finding bugs in circuits is difficult.

In the research and graduate courses at WashU, we have been using Synplicity's Identify tool to locate bugs in packet processing hardware. Based on our good experiences on this topic, I posted a tutorial from my class. The slides describe our network platform and show the methodology of how we debug of network hardware.

If you are teaching a debugging networking circuits or teaching a course on the topic, you might find the material below useful. I included both the PowerPoint and Adobe Acrobat versions of a presentation that I present in my courses.

Development of a System-On-Chip Extensible Network Processor and debugging using Identify, Acrobat format:

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or PowerPoint format:

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John Lockwood Reconfigurable Network Group

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Nice job. Thanks for the posting. I agree that debugging packet processing hardware is challenging. My bugs are most often due to missing a stimulus case or an assertion in the testbench.

Once I know the symptom, and if I am lucky, I can [1] find the event in the existing simulation waveforms. Then I can easily fix the offending code and and add an assertion to the testbench.

If I am unlucky, I have to [2] add stimulus cases to provoke the bug event. In the hopefully rare event that this can't be done I am reduced to [3] bringing out testpoints or [4] tainting the design with analysis hardware for signaltap, chipscope or identify debugging software.

So far 1, 2 and 3 have covered me. I am curious what other debugging methods you use and how identify compares to signaltap or chipscope for your projects.

-- Mike Treseler

Tutorial on debug of packet processing in FPGA hardware using Identify

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