Greetings, I am looking at an application that will provide an analog input signal in the 125 to 500 KHz frequency range, and wanted to convert it to a digital signal that would be processed by a Spartan 3 FPGA. I found two xilinx app notes that address issues related these areas (but based on Virtex FPGA):
My other hardware requirements are low power (nanoWatt). I am wondering if you can help me in the following areas:
- Is it possible to achieve these goals given the requirements (125-500 KHz input signal, low power consumption, Spartan 3)? Note: The input frequency cycles at 125 KHz. Thus my thought is if I can devise a circuit that perhaps operates at 500 KHz, that is sufficient tolerance to assume that within the 500 KHz range the 125 KHz can be assumed to be slowly changing or linear.
- My thought is that it is possible to implement these using Spartan
3, but the cited links were to Virtex architecture. What concerns come to mind for the transition?
- Reasonable expectations about the resolution/accuracy of such sampled analog signals?
(a) For example, I am only able to discretize the analog input signal into an 8 or 10 bit resolution (meaning that 2^8 is 256 output values for the vertical axis, thus it is an expectation for the measure of round-off errors).
(b) Eventhough the Spartan 3 can run at 50 MHz, the ADC would only be able to sample slowly changing signals (