Field-Programmable Gate Arrays

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nios2 / terminal

Hi, Do you have experience with nios2 and a specific terminal (hyperterminal, tera pro, or others) ?. I have problem to...
1 comments posted 21yrs
posted by bhb22l
1 comments posted 21yrs posted by bhb22l

Altera SCFIFO

Hi, I have generated two SCFIFOs with Altera Quartus (4.2 SP1) MegaWizardManager. One optimized for best speed (that is...
3 comments posted 21yrs
posted by ALuPin
3 comments posted 21yrs posted by ALuPin

FPGA Filter Design

Does anybody have filter design experience with FPGA? I would like to know a general picture with recent FPGA technolog...
8 comments posted 21yrs
posted by gpsabove
8 comments posted 21yrs posted by gpsabove

Post Translate Timing

Greetings, I have a situation where Post Translate timing is significantly different from behavioral/RTL simulation. I...
3 comments posted 21yrs
posted by yaseenzaidi
3 comments posted 21yrs posted by yaseenzaidi

Real Example of Xilinx IPCore Instantiation

Hi all, I'm having a hell of a time trying to use a Xilinx IPCore (DDS). I can generate the CORE, it seems I can instan...
2 comments posted 21yrs
posted by angilberto
2 comments posted 21yrs posted by angilberto

System Generator

Hi, I was wondering how can LVPECL/LVDS buffers be implemented in system generator. I am getting illegal buffer when I t...
0 comments posted 21yrs
posted by utrehcx
0 comments posted 21yrs posted by utrehcx

5 Volt tolerance - Altera

I am using a MAX II part in a new design with 3.3V supplies. I understand why the inputs might not be 5 volt tolerant....
9 comments posted 21yrs
posted by dsp
9 comments posted 21yrs posted by dsp

Speeding up FPGA designs

I'm looking for recommended practices for tuning my FPGA design. Merly cranking up the constraints and eyeballing the T...
2 comments posted 21yrs
posted by foobar
2 comments posted 21yrs posted by foobar

BIG PROBLEM : Configuration Boot Problem Stratix

hi, we've got some Stratix DSP development kit EP1S25 where at the power-on don't load the flash memory to the FPGA !!!...
4 comments posted 21yrs
posted by patrick.melet
4 comments posted 21yrs posted by patrick.melet

Xilinx MacFir5.0 - Block Ram requirenments

Hi all, I implemented a fir filter using the MacFir5.0 core from Xilinx. The filter 2 coefficient sets of 33 taps, with...
9 comments posted 21yrs
posted by nemesis2001
9 comments posted 21yrs posted by nemesis2001

How to reset a PLB/OPB Peripheral

Hi I would like to know how we can reset an OPB/PLB Peripheral during runtime. Thank you Joey
2 comments posted 21yrs
posted by johnsons
2 comments posted 21yrs posted by johnsons

ISE 7.1 Service Pack 2 - Ready yet?

I'm starting a new project at the moment, and I'm looking at upgrading to ISE 7.1, since I prefer not to change synth/p...
10 comments posted 21yrs
posted by jeremy
10 comments posted 21yrs posted by jeremy

use lattice and actel synplify together...

Is it possible to have for each tool an own license file path set? Lattice ispLever Base with synplify bites Actel Libe...
1 comments posted 21yrs
posted by me
1 comments posted 21yrs posted by me