Does anybody have filter design experience with FPGA? I would like to know a general picture with recent FPGA technologies like XtremeDSP and others. I am also curious about the limitation of FPGA design on filter design, like the maximum center frequency and bandwidth of the filters that can be implemented with FPGA. Could anybody let me know if I am able to simulate a SAW (surface acoustic wave ) filter with 185MHz center frequency and 4MHz double-side bandwidth, and Max. 20dB insertion loss inside of a FPGA?

Any information will be highly appreciated. Thanks in advance.

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Well, the Nyquist criteria indicates you will need an ADC operating at above 370 Megasamples/second, with sufficient number of bits at that frequency to give the signal to noise ratio required for your application. This may be the real problem. Depending on the type of filter required, I imagine some of the higher-end FPGAs could handle the arithmetic at this rate, although some multiplexing of resources might be required. Then, a DAC with the same sample rate and sufficent bits for reconstruction of the signal will be needed after the FPGA.

Hmm, SAW filters are generally used in narrow bandpass applications. The Nyquist criterion says you need a sample rate double the bandwidth you're interested in. It may be that you can reduce the necessary sample rate considerably by only focussing on the band of interest. At the very least, once you've sampled the data, you could decimate considerably to concentrate your processing on the band of interest. I suggest reading about multirate DSP. Cheers, Syms.

I think he means that after sampling, there's a data stream going through the FPGA at 370MHz (if we do need to stick to the Nyquist frequency). This is possible, but not easy to sustain. Therefore, if the algorithm allows it, it may be easier to split (multiplex) the data into a number (say 4) of data streams running at the inversely reduced (i.e. 1/4th in this case) frequency, possibly recombining (demultiplexing) the sample streams after some sort of decimation.

The FPGA doesn't limit your filter design other than max sample rate (and even then there are work-arounds). The DSP48 slices in Xilinx Virtex4 can do 500 MS/Sec filters provided the data and coefficients are

18 bits or less and you choose a device with enough DSP48 slices to fit one slice per filter tap. Remember, an FPGA is simply a medium in which you realize a digital logic circuit.

As to your particular example, you've got a rather narrow bandpass filter. Filtering such a narrow band relative to your sample rate is going to require a high order filter (assuming FIR filter in order to get the linear phase characteristic of the SAW) if you insist on doing the filtering at the input sample rate. It is far more efficient to downcovert the signal to complex baseband, filter it with a 4 MHz low pass filter and then upconvert it back up to your 185 MHz center frequency. This way, the filter has a much wider passband relative to the sample rate, and therefore is much simplier to realize, both in terms of number of taps (coefficients) and in data rate. The hardest part of this design would be digitizing the data and getting it into the FPGA, and that is quite doable.

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--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.

Is it hard to design a down-converter and a up-converter inside of FPGA? I do not have experience to design converters. Will the converters take lots of resources of FPGA?

Depends on your experience I suppose. I don't think it is hard, but others may find that it is. The resource usage depends on several factors: What is the data rate? what is the required SNR? What is the bandwidth relative to the sample rate? How much out of band filtering is required? What is the ratio of the input and output sample rates? Perhaps the largest determinant is the filter architecture. Using a multi-rate architecture results in substantial area savings.

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--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.

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