I have a situation where Post Translate timing is significantly different from behavioral/RTL simulation. I am not not speaking of simple delays, the outputs/data are different than what they should be.
What is interesting is that the design works on the FPGA board. I implemented a serial port in loopback mode in Xilinx, if I type a character on Hyperterm I get the same returned from the FPGA.
I have set timing constraints but to no effect.