Real Example of Xilinx IPCore Instantiation

Hi all, I'm having a hell of a time trying to use a Xilinx IPCore (DDS).

I can generate the CORE, it seems I can instantiate it (not sure -- verilog/fpga newbie).

Everything seems to be ok, but I get no output -- like the output pins are not connected to module's sin/cos output...

Can anyone provide a sample (small one) code showing how to really instantiate a CORE into a Verilog projet ?

Thank you,


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When you generate a core in ISE, the CoreGen tool creates a file with your module name and extension .veo (so if your core is called my_dds, you should have a file called my_dds.veo) In this file is an instantiation template for the CoreGen module. It may look like:

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG my_dds YourInstanceName ( .DATA(DATA), .WE(WE), .A(A), .CLK(CLK), .ACLR(ACLR), .RFD(RFD), .RDY(RDY), .SINE(SINE), .COSINE(COSINE));

// INST_TAG_END ------ End INSTANTIATION Template ---------

In Verilog you can't tell from the template which ports are ins, outs, vectors, scalar. You can find this information if you look into the generated simulation module my_dds.v

Here you may find something like:

module my_dds( DATA, WE, A, CLK, ACLR, RFD, RDY, SINE, COSINE ); // synthesis black_box

input [27 : 0] DATA; input WE; input [4 : 0] A; input CLK; input ACLR; output RFD; output RDY; output [5 : 0] SINE; output [5 : 0] COSINE;

If you're using the project navigator, an easy way to see how to instantiate the module is to go to Project-->NewSource and make a new Verilog TestFixture associated with my_dds. This will generate a file with the instantiation template and registers and wires for the modules inputs and outputs. It may look like:

module my_dds_test_dds_v_tf();

// DATE: 14:54:07 06/21/2005 // MODULE: my_dds // DESIGN: my_dds // FILENAME: test_dds.v // PROJECT: FastVideo1 // VERSION:

// Inputs reg [27:0] DATA; reg WE; reg [4:0] A; reg CLK; reg ACLR;

// Outputs wire RFD; wire RDY; wire [5:0] SINE; wire [5:0] COSINE;

// Bidirs

// Instantiate the UUT my_dds uut ( .DATA(DATA), .WE(WE), .A(A), .CLK(CLK), .ACLR(ACLR), .RFD(RFD), .RDY(RDY), .SINE(SINE), .COSINE(COSINE) );

// Initialize Inputs `ifdef auto_init

initial begin DATA = 0; WE = 0; A = 0; CLK = 0; ACLR = 0; end



Obviously the code at the bottom is for simulation only, but the uut instantiation and the reg's and wires should work with synthesizable code.

H> Hi all,

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Terrifc, Gabor. Thank you very much for the TIPs (Capital tip) -- I'll take a closer look into it.


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