1. Home
  2. Field-Programmable Gate Arrays
  3. BIG PROBLEM : Configuration Boot Problem Stratix

BIG PROBLEM : Configuration Boot Problem Stratix

hi,

we've got some Stratix DSP development kit EP1S25 where at the power-on don't load the flash memory to the FPGA !!!

We've seen that the EPLD MAX 7064 often fail the programmation of the FPGA...

We've seen that the RESET of this EPLD is in the same time that the

3.3 V power-on...

Did someone have this this problem yet... and how to boot at any time on power-on ?

Perhaps it's be better if the RESET is after the 3.3V power-on ?

We utilizes 3 board in a big system and we have this problem now of non programming at boot..

Thanks

Reply to
Patrick
Loading thread data ...

"Patrick" schrieb im Newsbeitrag news: snipped-for-privacy@posting.google.com...

Use a voltage monitor that releases the reset after ALL voltages are valid.

Regards Falk

Reply to
Falk Brunner

We add a RC circuit beetween the reset from the Stratix circuit to the MAX circuit. So the MAX is resetted after the 3.3V is ON and sometimes the program from the flash don't boot !!! This is a big problem for our system which uilizes 3 boards... My Support from Altera don't explain me what's happen...

So is there anybody who have this problem with these EP1S25 cards and is there a solution ?

Reply to
Patrick

"Patrick" schrieb im Newsbeitrag news: snipped-for-privacy@posting.google.com...

So why to safe a buck to get a REAL voltage monitor. Do it and try. And see.

Regards Falk

Reply to
Falk Brunner

For those who have the same problem. Altera have new files for reprogramming the MAX chip. And so the card will boot at every power-up. The release is dated by 13 June 2005 !!!!

Reply to
Patrick

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.