I'm looking for recommended practices for tuning my FPGA design. Merly cranking up the constraints and eyeballing the TA output doesn't seem to work very well for non-trivial problems (I find it very hard to relate back to my RTL).
Presumedly the better approach is to work on submodules though timing estimates for individual modules are highly likely to be too optimistic as they do not account for inter-module connections and competition for resources.
I vaguely remember reading about in a Xilinx app note how they had two versions of a particular module (an SDRAM controller?), one for real use and one for estimating the performance. The difference IIRC was that input and output were registered.
Any suggestions?
Thanks, Tommy -- fpga at numba-tu dot com