Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

Retrieving code from an old PAL

Dear All, I have to duplicate a board that was designed by our company 18 years ago. It has a PLS101 PLA on it. Unfortu...
2 comments posted 21yrs
posted by boothmultipler
2 comments posted 21yrs posted by boothmultipler

FPGAs: Where will they go?

Hi All, I have some general questions related to FPGA. What do people in this forum see is the future of FPGA 4 to 5 ye...
21 comments posted 21yrs
posted by lovesinghal
21 comments posted 21yrs posted by lovesinghal

Xilinx LPT programmer help

hello all, I've built my own Xilinx parallel cable as described here: http://www.xilinx.com/support/programr/jtag_cable...
0 comments posted 21yrs
posted by toto
0 comments posted 21yrs posted by toto

Xilinx webshop

Following the Spartan 3 availability threads, I visited the Xilinx webshop. The only FPGA on offer there is the Spartan...
14 comments posted 21yrs
posted by sorry
14 comments posted 21yrs posted by sorry

Microblaze address space and variables

Hallo, I must create a memory for a display lcd. This is part of a microcontroller based on microblaze. I thought to do...
12 comments posted 21yrs
posted by marcotoschi
12 comments posted 21yrs posted by marcotoschi

Spartan 3 availability

Further to recent discussiuons here, I Just noticed That S3s have appeared in the Xilinx web store. A few are even shown...
5 comments posted 21yrs
posted by mike
5 comments posted 21yrs posted by mike

globally asyncronous vs locally syncronous?

Hi I implemented simple VHDL-written processing node (processor, BRAM, memory controller and network controller). And I...
2 comments posted 21yrs
posted by pasacco
2 comments posted 21yrs posted by pasacco

Lattice LFEC

Hello.. Is this normal that same core which performs well for Altera Cyclone device can only run at half speed on a LFE...
10 comments posted 21yrs
posted by me
10 comments posted 21yrs posted by me

clock domain : DDR read enable

Hi, I am doing a DDR-controller, using a delayed version of the Data strobe to capture the data, however my main proble...
0 comments posted 21yrs
posted by bibo1978
0 comments posted 21yrs posted by bibo1978

damage Atmel AT40k/AT94k with wrong bitstream?

Hey, does anybody know if you can damage Atmel's newer FPGAs with a bad bitstream (ie vdd-to-ground contention)? There'...
7 comments posted 21yrs
posted by megacz
7 comments posted 21yrs posted by megacz

Ideal CPU for FPGA?

In an unrelated thread on FPGACPU clock speeds, an FPGA developer stated that FPGAs are ill suited to replicating legac...
11 comments posted 21yrs
posted by dave
11 comments posted 21yrs posted by dave

CPLD fusemap data - why the secrecy?

I have been using the Coolruner for some time now. I use tools which I have written so I needed the programming data; b...
17 comments posted 21yrs
posted by dp
17 comments posted 21yrs posted by dp

SystemC comments

I recently attended an FPGA vendor seminar that included some discussion of SystemC, HandelC and MentorGraphicsC. I tri...
3 comments posted 21yrs
posted by Fougueux
3 comments posted 21yrs posted by Fougueux

Interesting question on CPLD

Hi, can we disconnect the power suppy to some Macrocells which are not using in the design or functionality for a perti...
4 comments posted 21yrs
posted by himassk
4 comments posted 21yrs posted by himassk

circuit optimization - a feedbackless machine

Lets consider an abstract machine generating a new word from in a finite space at every its step in a deterministic way...
5 comments posted 21yrs
posted by spam
5 comments posted 21yrs posted by spam