Field-Programmable Gate Arrays

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NIOS II + USB 2.0 host

Hi, We will soon be using the Nios II as embedded controller and we would like to add a High Speed (HS) USB 2.0 hosting...
6 comments posted 21yrs
posted by bjskill
6 comments posted 21yrs posted by bjskill

How to Interface External Ram with FPGA

If any one has idea about interfacing external RAM with Sparton-2 ,,,,,,,,Then Plz guide ............as i need it in my...
1 comments posted 21yrs
posted by fahadislam2002
1 comments posted 21yrs posted by fahadislam2002

Bus Macros

To my understanding, bus macros are tri-state buffers at relative fixed positions according to XAPP290. I'd like to imp...
5 comments posted 21yrs
posted by Hua.Zheng
5 comments posted 21yrs posted by Hua.Zheng

Doubts on Xilinx FPGA

Hello all, Is there any way i can initialise values into the Xilinx FPGA FF. I am working on the Virtex E FPGA. Please t...
11 comments posted 21yrs
posted by vssumesh_asic
11 comments posted 21yrs posted by vssumesh_asic

Why cann't this block be synthesized in top level

I create a module then synthesize it.Everything goes well. But when I call it in upper block,my synthesis tool tell me...
6 comments posted 21yrs
posted by qx0103
6 comments posted 21yrs posted by qx0103

Wanted: I2C RAM pre-loader VHDL module

Hi, Since the Actel RAM modules cannot be preloaded a program time, I need a module that will read data from an I2C ser...
2 comments posted 21yrs
posted by scd
2 comments posted 21yrs posted by scd

Modulo division in Verilog

Hi Guys, I have run into a problem that I was not expecting, I need to calculate the remainder after division (modulo)...
8 comments posted 21yrs
posted by psolomon
8 comments posted 21yrs posted by psolomon

Wanted Actel ProAsic RAM VHDL models

Hi, I've tried inferring RAMs, but it doesn't seem to work well, so I want to just instantiate the Actel RAM primitives...
1 comments posted 21yrs
posted by scd
1 comments posted 21yrs posted by scd

Reading a PS/2 mouse

I have some source codes that should be able to read a mouse through the PS/2 port on the Xilinx fpga board; it sends $...
6 comments posted 21yrs
posted by greenplanet
6 comments posted 21yrs posted by greenplanet

Virtex 300: what could cause pin to short?

I'm trying to find out what could cause a pin in a Virtex 300 part to short out. It's happened more than once, within a...
5 comments posted 21yrs
posted by rjmyers
5 comments posted 21yrs posted by rjmyers