Wanted Actel ProAsic RAM VHDL models

Why don't you use ACTGEN? If you have access to Precision then the example below will infer a synchronous memory block,

-------------------------------------------------------------------------------

-- Actel Synchronous Memory

------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; -- yes I know, shouldn't use it :-)

entity ssram is port( clk : in std_logic; din128 : in std_logic_vector (127 downto 0); addr : in std_logic_vector (3 downto 0); we : in std_logic; dout128 : out std_logic_vector (127 downto 0) ); end ssram ;

architecture rtl of ssram is

type mem_type is array (15 downto 0) of std_logic_vector(127 downto 0) ; signal mem : mem_type;

begin

singleport : process (clk) begin if (clk'event and clk = '1') then if (we = '1') then mem(conv_integer(addr))