Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

ise 7.1 Input clk is never used.

i'm just starting out with fpgas and i'm having what's probably a basic newbie problem. i have the following simple ent...
6 comments posted 21yrs
posted by jeff.murphy
6 comments posted 21yrs posted by jeff.murphy

Problems programing FPGAs..

I am having problems programming the FPGAs I have on board. Well I have two FPGAs on board a XC3s400 (Spartan 3) and xc...
2 comments posted 21yrs
posted by shailesh.radhakrishnan
2 comments posted 21yrs posted by shailesh.radhakrishnan

Implement a JTAG controller in an FPGA

Anyone done a JTAG controller in VHDL or Verilog? I want to use an FPGA to program another JTAG device. Cheers, Irish
2 comments posted 21yrs
posted by decalternate
2 comments posted 21yrs posted by decalternate

NIOS2 toolchain sources...

Huomenta (o; Looks like Altera listened to me and released the NIOS2 toolchain sources on their ftp server finally (o;...
2 comments posted 21yrs
posted by me
2 comments posted 21yrs posted by me

edif version generated by xilinx ISE 6.2

Hi all, I am trying to find the edif version used by Xilinx ISE 6.2.03i generated by XST. Also I was wondering if somebo...
0 comments posted 21yrs
posted by alatath
0 comments posted 21yrs posted by alatath

MAPLD 2005: Program Announced and Registration Open

Program Announced --- Registration Open 2005 MAPLD International Conference Ronald Reagan Building and International Tr...
0 comments posted 21yrs
posted by richard.b.katz
0 comments posted 21yrs posted by richard.b.katz

Safe State Machine Design in AHDL

Hello, I was curious if anyone can comment on writing safe state machines in AHDL. I often use One-hot encoding in my s...
1 comments posted 21yrs
posted by jjlindula
1 comments posted 21yrs posted by jjlindula

16-bit Acesses on ISA bus

Hello! I have card which generate 16-bit ISA bus timing. I like to know if ISA bus in 16 bit generates address bus sequ...
2 comments posted 21yrs
posted by sinebrate
2 comments posted 21yrs posted by sinebrate

Xilinx Conversion 3.1 --> 6.1

Hi all, i have an old xilinx project developed with version 3.1 (schematic file) Now i work with Xilinx Project Navigat...
5 comments posted 21yrs
posted by softwareNOSPAM
5 comments posted 21yrs posted by softwareNOSPAM

Xilinx PLEASE HELP

why is it so that whatever I do, I am stuck with (Xilinx) problems?! I need urgently, within 2 days to implement a prog...
3 comments posted 21yrs
posted by antti
3 comments posted 21yrs posted by antti

FPGA to ASIC + JTAG chain insertion

Hi all, We have to do a FPGA-to-ASIC conversion with JTAG chain insertion. The design was tested on spartan-II and was...
0 comments posted 21yrs
posted by laurent.gauch
0 comments posted 21yrs posted by laurent.gauch

Clock recovery in FPGA at 300 MHZ

Hi all, I want to implement a clock extraction circuit from data at 300 Mbps. What i wanted to know is that is it reall...
3 comments posted 21yrs
posted by praveen.kantharajapura
3 comments posted 21yrs posted by praveen.kantharajapura

Unrolled Pipeline Implementation

Hi Guys, I am writing some verilog to implement an unrolled pipeline for a vector mode cordic function. What I end up h...
3 comments posted 21yrs
posted by psolomon
3 comments posted 21yrs posted by psolomon