I create a module then synthesize it.Everything goes well. But when I call it in upper block,my synthesis tool tell me there is some logic cannot be synthesized. I do all my work in ISE6.3i. Why does this happen? And how should I deal with it thx
Can you tell us what modules are you talking about ?
What is the entity and port declaration of the sub module ? How is the port map in the top level module ?
Rgds
i write a frequency division module(name it "pre_freq_div") in order to output different frequency related to the division coefficient input,and the coefficient may be large(14-bit). this module get synthesized correctly independently. i also simulate it in modelsim se 6.0, the wave is perfect, i think. But when this module is getting into use from top level design,the systhesis tool tell me: Synthesizing Unit . Related source file is pre_freq_div.v. Register equivalent to has been removed ERROR:Xst:739 - Failed to synthesize logic for signal . ERROR:Xst:1431 - Failed to synthesize unit .
module pre_freq_div(clk,_reset,div_coef,freq_out); input clk,_reset; input [13:0] div_coef; output freq_out; reg freq_out; reg [13:0] counter;
always @ (posedge clk) begin if(_reset==0) begin freq_out=0; counter=0; end else begin if(div_coef==14'b0) freq_out=0; else begin if(counter!=div_coef) begin counter=counter+1; freq_out=freq_out; end else begin counter=0; freq_out=~freq_out; end end end end
endmodule
This error bothers me. how can , a 14-bit vector be equivalent to , a scalar value? This seems to be a clue. There's nothing obviously wrong with the code in this module, so I'd think there's a problem with the instantiation at the top level. The first place I'd look is the reset input, which is one thing that could cause to be equivalent to . Is it possible that XST doesn't like a leading underscore in the module input _reset? Also _reset is active low. Did you by mistake tie it to zero or leave it out of the port list at the top level?
Another thing that could cause this is the lack of a clk input to the module. Also if div_coef is zero. I think we'd need to see the instantiation code to find the problem.
_reset is a global input signal,so it won't be influenced by the upper leven unit,i think. i simulated and synthesized the module independently,it all went well,so i don't think an underscore makes any differents.
Hi,
I think the way code is written might be the problem. In the following line:
if(div_coef==14'b0) freq_out=0;
the status of the counter signal when the condition (div_coef==14'b0) is met is not specified. This might be throwing the synthesizer off the track.
Modify the line as
if(div_coef==14'b0) begin freq_out=0; counter = 14'b0; end
then try synthesizing.
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