Doubts on Xilinx FPGA

Hello all, Is there any way i can initialise values into the Xilinx FPGA FF. I am working on the Virtex E FPGA. Please tell me how can i achive that through verilog. Thank you

Reply to
vssumesh
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Any flip-flop that has an asynchronous reset or preset term will be initialized automatically when the FPGA is loaded from the bitstream. The standard templates for flip-flops are available in the Language Templates options of ISE.

Menu: Edit --> Language Templates...

Navigate to: Verilog --> Synthesis Templates --> Flip Flops --> D Flip Flop with Asynchronous Reset

This shows the standard template for inferring flip-flops with initialization.

Note that any flip-fl> Hello all,

Reply to
Gabor

Aside from the asynchronous clear or preset, some synthesizers will accept register initialization such as:

reg [7:0] count = 8'h1c; always @( posedge clk ) count

Reply to
John_H

What will be the status of F/F and internal block RAMs of VirtexE FPGA if i do not specify any initial condition. Can i assume that it is zero ?

Reply to
vssumesh

What will be the conditions of the F/F and internal block RAM if i didnt specified any initial value. Can i assume that its zero ??

Reply to
vssumesh

Internal BlockRAMs will initialize to zero unless you specify other values. Some BlockRAM outputs (but not on Virtex-E) have an initial state for the synchronous output specifiable.

The initial state of the registers is a little less obvious. If a register is preset without a clear or set without a reset (using the S/R input) the register will initialize high. If a register isn't preset or set, it will initialize low. This includes registers that are reset, cleared, or have no S/R control.

I use the terms "preset" and "clear" for asynchronous events and "set" and "reset" for synchronous.

Reply to
John_H

Dear john... Please tell me the reset condition of internal counters. Is there any way to initialize the counter also with preset values.

Reply to
vssumesh

"Dear john" ...my oh my.

Counters are registers.

1) You can always use the INIT=S and INIT=R attributes on the individual bits of the counter word in your ucf file. 2) If you're using XST, you might be able to use the initial definition reg [7:0] counter = 7'ha5; // to initialize to hex value a5 3) If you're using Synplify, see 1). 4) If you're using something else I can't help you any further.

Reply to
John_H

Ummmm, how about this simplest, and most portable way?

always @(posedge clk or negedge rst_l) begin : FlopWithInit if (~rst_l) begin q

Reply to
Andy Peters

You don't really need a reset signal, just a reset process. The flip-flop you designed could be instantiated with rst_l tied high at a higher level of hierarchy, but the initialization value after download would still match the value from the reset process.

Reply to
Gabor

Hi john... I tried the first way but it did gave an error. But the second method did not gave an error but i dont know whether it is initialised prperly. The set pin is still tied to the ground. Can we assume that the stet is '1' ? Sorry for this late replay.... regards Sumesh

Reply to
vssumesh

You could use FPGA Editor to look at the slice or IOB with the register in question. There are boxes to indicate power-up high or low and S/R high or low.

You could also look at your edif output produced by Synplify to make sure the INIT=S property is attached to your instance. If you're *not* using Synplicity tools, the "synthesis xc_props" directive would probably be ignored by the synthesizer. No error, no effect.

Reply to
John_H

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