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Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?

Does anyone know where I can find a public domain / open source tool that will read a bunch of VHDL and/or Verilog files, and generate a block diagram from them?

VGUI-2

formatting link
will generate VHDL from block diagrams; the reverse process was listed as a future enhancement, but the latest update seems to be two years old.

Does anyone know if the Hierarchy Surfer script (at

formatting link
has been updated (since

2000) and posted anywhere for the general public?

Has anyone adapted an older version of Hierarchy Surfer to generate block diagrams?

Thanks 2^32 for your help...

mj

Reply to
jjohnson
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I don't think there is one. Quartus/Mentor/Synplicity have an hdl viewer that can do entity boxes and wires. Modelsim has a data flow viewer that shows processes and signals.

What would you do with this diagram if you had it?

If the aim were to learn a design by others, I would write a testbench and watch it run on a simulator.

If the aim were to document the design, I would do it as comments in the source and testbench code.

-- Mike Treseler

Reply to
Mike Treseler

I document testcases as comments with a special prefix. These are then filtered out and processed with LaTeX, giving a nice PDF file. One could also embed diagrams in description languages like pstricks, metapost, dot, pic etc. and handle them in the same way. If somebody has already done this, I'd love to hear about it.

To the original poster: take a look at emacs' vhdl-mode and its integration into speedbar for a hierarchy parser.

Cheers, Colin

--
If God had not given us sticky tape, it would have been necessary to
invent it.                                              [Pete Zakel]
Reply to
Colin Marquardt

I have found the Quartus RTL Viewer a tremendous help in developing a feel for what logic would be generated by what code. It is also immediately obvious if one has left out a default value for a case structure and other simple errors that make a huge difference in the generated logic.

It has also been useful where clients have insisted that they want a schematic version of the EPLD code.

Regards Anton Erasmus

Reply to
Anton Erasmus

Sounds like what doxygen does for C++ code. Has anyone written a verilog parser for doxygen? Regards Jahagirdar Vijayvithal S

Regards Jahagirdar Vijayvithal S

--
If a man does only what is required of him, he is a slave. If a man does more
than is required of him, he is a free man.  --Chinese Proverb
Jahagirdar .V.S
IC Design Engineer , Texas Instruments (India) Ltd.
91-80-25099129(O) 91-80-28540394(R)
Reply to
Jahagirdar Vijayvithal S

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