Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?

I don't think there is one. Quartus/Mentor/Synplicity have an hdl viewer that can do entity boxes and wires. Modelsim has a data flow viewer that shows processes and signals.

What would you do with this diagram if you had it?

If the aim were to learn a design by others, I would write a testbench and watch it run on a simulator.

If the aim were to document the design, I would do it as comments in the source and testbench code.

-- Mike Treseler

I document testcases as comments with a special prefix. These are then filtered out and processed with LaTeX, giving a nice PDF file. One could also embed diagrams in description languages like pstricks, metapost, dot, pic etc. and handle them in the same way. If somebody has already done this, I'd love to hear about it.

To the original poster: take a look at emacs' vhdl-mode and its integration into speedbar for a hierarchy parser.

Cheers, Colin

I have found the Quartus RTL Viewer a tremendous help in developing a feel for what logic would be generated by what code. It is also immediately obvious if one has left out a default value for a case structure and other simple errors that make a huge difference in the generated logic.

It has also been useful where clients have insisted that they want a schematic version of the EPLD code.

Regards Anton Erasmus

Sounds like what doxygen does for C++ code. Has anyone written a verilog parser for doxygen? Regards Jahagirdar Vijayvithal S

Regards Jahagirdar Vijayvithal S