Hi, I know virtex-4 has 32 global clock lines and there is a requirement that from any clock region, I can use up to 8 glock lines.
Is there any visualized way so that I can see what is the coverage of each clock region for a particular chip? Or some table kind of listing each clock region covering which IO pins?
Thanks.
schrieb im Newsbeitrag news: snipped-for-privacy@g49g2000cwa.googlegroups.com...
look at the docs, for Spartan 3E the global clocks are explained pretty nicely, with color pictures and charts
the clocks are not bound to (covering) IO pins, rather there are 8 BUFG muxs that drive 8 lines that enter a single clock quadrant. there are of course limitations of what clock sources can be routed to those BUFGs
antti
schrieb im Newsbeitrag news: snipped-for-privacy@g49g2000cwa.googlegroups.com...
I was referring to pagr 49 in DS312.pdf s3e complete datasheet, i assume similar figure should be in v4 ds as well
antti
Hi in the PACE tool you can select "Show Clock Regions". Or you look in the FPGA editor and search the BUFR buffers ans select an output of this.
florian
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