Field-Programmable Gate Arrays

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Re: Soft IPs licensing -gpl

> Hi all, > > I am looking for information about licensing of HW designs. I read on the OpenCores web site that > they...
0 comments posted 21yrs
posted by josephhenryblack
0 comments posted 21yrs posted by josephhenryblack

Digilent's JTAG-USB cable with chipscope

Can one use the JTAG-USB cable from digilent with chipscope ? Sumit
7 comments posted 21yrs
posted by do_not_reply_to_this_addr
7 comments posted 21yrs posted by do_not_reply_to_this_addr

Logic lab programmer

Hi, I will repost the message I recovered posted in 1998 and modify it a little. I've got a fairly old Lattice GAL prog...
0 comments posted 21yrs
posted by geert
0 comments posted 21yrs posted by geert

chipscope and V2P problems

I'm working with avnet v2p dev board trying to communicate with the device via the pci bus right now i want to see if a...
1 comments posted 21yrs
posted by wallge
1 comments posted 21yrs posted by wallge

XST and TCL support?

Does XST 7.1 support TCL scripting? I don't see any mention of it in the XST User Manual and I find the command line mo...
6 comments posted 21yrs
posted by killerhertz
6 comments posted 21yrs posted by killerhertz

Synplify 8.1 - View Synthesis Report

Hi I am using Xilinx ISE 7.1.02i and Synplify 8.0; recently updated t Synplify 8.1 Synthesizing the VERILOG cod `timesc...
1 comments posted 21yrs
posted by h.gaedke
1 comments posted 21yrs posted by h.gaedke

GLCKs on Spartan3

Hi everyone, in my design on a Spartan3 there are 9 GCLKs used, but there are only 8 available. Is the number of GCLKs...
3 comments posted 21yrs
posted by holzi_stefan
3 comments posted 21yrs posted by holzi_stefan

Remove Duplicate Registers / Logic

Hi, in Quartus there is an option "Remove Duplicate Registers / Remove Duplicate Logic". Is there something similar in...
3 comments posted 21yrs
posted by ALuPin
3 comments posted 21yrs posted by ALuPin

How to import a netlist in VHDL

Hi everyone, I have a VHDL file which I use it in EDK in one of my custom cores ..I also have a netlist file which has...
1 comments posted 21yrs
posted by beeraka
1 comments posted 21yrs posted by beeraka

dual port ram

Hey folks, OK, I'm feeling a little silly here. I'm trying to use a dual port ram in a xilinx v2p device, and I'm havin...
0 comments posted 21yrs
posted by maplante
0 comments posted 21yrs posted by maplante

Delay Generators in FPGAs

Hi: I have been tasked to build several custom laboratory instruments. One is a "safety system" for some engine combust...
7 comments posted 21yrs
posted by crcarleRemoveThis
7 comments posted 21yrs posted by crcarleRemoveThis

No clock signals found in this design... XST V2P

I have a top level design with a clock this clock goes into an into a DCM and then into a submodule where the dcm divid...
1 comments posted 21yrs
posted by wallge
1 comments posted 21yrs posted by wallge

chipscope/impact Virtex4 problem

Hey all, I just made a V4 pcb and wanted to configure the FPGA through impact => this works fine, so it says that the d...
4 comments posted 21yrs
posted by tim.verstraete
4 comments posted 21yrs posted by tim.verstraete

stratix gx query

hi all, we are trying to implement a QAM 64 system using the altera stratix gx for a project. all of us are new to fpga...
1 comments posted 21yrs
posted by fidodido93
1 comments posted 21yrs posted by fidodido93