Latest threads in Field-Programmable Gate Arrays

wishbone core with ethernet, hierarchy / architecture

Hello, I am pretty new to working with FPGAs and verilog in general but have a decent knowledge of programming, and Im...

0 21yrs

mwiesbock

0 21yrs mwiesbock

simulatable but not synthesizable (verifiable)

Dear I am synthesizing and mapping following examples (counters) into Vertex II pro with ISE6.3. Both of them are worki...

3 21yrs

pasacco

3 21yrs pasacco

Reset and Power-On Reset Activation XCFxxP PROMs

Hi, If you read the specs of the XCFxxP PROMs, you find: http://www.xilinx.com/bvdocs/publications/ds123.pdf (page 22 o...

2 21yrs

Pablo.Alvarez.Sanchez

2 21yrs Pablo.Alvarez.Sanchez

bmm file and ramb16

Hello, I have 2 32x512 brams. I'm using the parity bits to extend the available data out a couple extra bits, so I can...

3 21yrs

maplante

3 21yrs maplante

question for Xilinx ppl

Hello all, This issue has been here for a few times, so... I was wondering if there is a progress with an issue of port...

2 21yrs

muravinv

2 21yrs muravinv

isplever and GAL

Hi everybody, I bought the isplever 5.0 to develope a project with a lattice cpld, serie ispmach. I used the schematic...

4 21yrs

olmirko

4 21yrs olmirko

QuartusII 4.2 problem

Hello, We are using Altera QuartusII 4.2 software and we have a problem when we create symbols and use the symbols on t...

2 21yrs

monica_dsz

2 21yrs monica_dsz

Datasheet error in the Altera Cyclone 2C8F256 pindescription

After having mailed Altera which forwarded the mail to whoever... BTW it was rather hard to find an email adress at all...

9 21yrs

none

9 21yrs none

WEB Pack 7.1 and registry access

Hi all, It seems the WEB Pack 7.1 SP3 needs to write into registry after every start in order to work properly. If regi...

0 21yrs

ymonyak

0 21yrs ymonyak

how to measure number of cycles in ISE6.3

hi I need to measure "number of clock cycles" or "execution time", after mapping the VHDL code into Vertex II pro. In M...

1 21yrs

JEmoderatz

1 21yrs JEmoderatz

Conversion of ASIC RTL to FPGA RTL

Hi all, Can any one list me out the various steps that need to be carried out to convert ASIC RTL Code to FPGA RTL Code...

4 21yrs

sarath1111

4 21yrs sarath1111

Xilinx Foundation ISE and WinXP/x64?

Just curious, does Foundation ISE support XP/64? Is the program capable of addressing more than 2GB of RAM?

2 21yrs

hpg

2 21yrs hpg

ISE makes a mistake

Hi, something really strange just happened. I tried to generate a testbench waveform to simulate on modelsim and models...

1 21yrs

skatoulas

1 21yrs skatoulas

LVDS problem/chipscope VIRTEX4

Hey, I just got a board with a virtex4 and there is a LVDS connection on it and another LVDS input bank where the clock...

0 21yrs

Yttrium

0 21yrs Yttrium

The new IOBUF in Spartan-3E

Hi guys, Has anyone tried instantiating IOBUF in a Spartan-3E device? The IOBUF primitive for S3E has two new attribute...

1 21yrs

george.mercury

1 21yrs george.mercury

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