Digilent's JTAG-USB cable with chipscope

schrieb im Newsbeitrag news: snipped-for-privacy@g43g2000cwa.googlegroups.com...

ChipScope only works with officially supported Xilinx cable, and does not work with 3rd party cable to it is not 100% compliant to fully supported cable.

It could be possible to write 'ChipScope' server that would allow to use 3rd party cable, but would require reverse engineering of the protocol used by the ChipScope server.

Antti

Humm... Why wouldn't Xilinx support this cable (I thought Digilent and Xilinx have a close relationship) and if not Why wouldn't Xilinx publish the protocols used by Chipscope server. Are they trying to make money by selling their own expensive USB cable ?

Sumit

schrieb im Newsbeitrag news: snipped-for-privacy@o13g2000cwo.googlegroups.com...

The Xilinx - Digilent co-oper is not so close.

Xilinx is NOT publishing the ChipScope server protocol and Xilinx is NOT publishing the Impact server protocol

because they may change those with every service pack and the do not want additional hassle from 3rd parties. Maybe some other issues as well.

Yes, it looks like Xilinx is trying to make money on the over priced USB Cable, that doesnt work very good. The PCs with LPT port are coming to be 'hard to get' items, so the only official cable is Xilinx USB cable, what is very EXPENSIVE, it only contains Cypress 68013 and Coolrunner, but cost

Antti

"Antti Lukats" schrieb im Newsbeitrag news:dcn3ss$qou$04$ snipped-for-privacy@news.t-online.com...

is

UUPS! I made a mistake - the USB cable is $149 not 495, so its not so bad deal at all. (some other FPGA vendor sells USB cable for 400+ USD so I messed up)

sorry.

Antti PS we are using the Xilinx USB cables all the time now.

Did you mean that the cable doesn't work very well, or that trying to make money on it doesn't work very well? I hope you meant the latter, since I'm considering buying one.

Seems not completely unreasonable.

Eric

Indeed - for US$150 it's a good deal. It's a USB2.0 High Speed cable that can handle 25Mbps through the JTAG port. I just got one two weeks ago and, after struggling a bit to understand how to get ChipScope Pro running properly, promptly debugged and verified a Spartan 3 VHDL design written by someone else. Not bad for an old Altera AHDL weenie, if I say so myself.

Thanks for a fine toolset, Xilinx!

Jim Horn, Sonoma County California