Hi
I am using Xilinx ISE 7.1.02i and Synplify 8.0; recently updated t
Synplify 8.1
Synthesizing the VERILOG cod
`timescale 1ns / 1p
module adder4_simple
input wire CLK input wire [7:0] IN_1 input wire [7:0] IN_2 input wire [7:0] IN_3 input wire [7:0] IN_4 output reg [9:0] OU )
always @(posedge CLK) begi
OUT