I have a top level design with a clock this clock goes into an into a DCM and then into a submodule where the dcm divided clock is monitored with a process statement. and is used with a rising_edge(clk) statement as well
yet ISE (XST) still tells me there is no input clock signal what the heck is going on? do i need to change some synthesis settings? please help
code below:
library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all;
-- synthesis translate_off library UNISIM; use UNISIM.VCOMPONENTS.all;
-- synthesis translate_on library XilinxCoreLib;
-- V2P has 198 KB of BRAM
--roughly 50,000 double words
entity system is port ( OPB_Clk : in std_logic; --driven by 100mhz clk
SYS_RESET : in std_logic;
-- all these are big endian A : out std_logic_vector(0 to 31); --A, OE, WE, D are shared flash & sram OE_L : out std_logic; --WE_L : buffer std_logic; WE_L : out std_logic; D : inout std_logic_vector(0 to 31);
SRAM_CS_L : inout std_logic; SRAM_BS_L : out std_logic_vector(0 to 3); -- "bs" signals control "BLE#" and "BHE#"
TRGT_IRQ : in std_logic;
SYS_ACE_CS_N : out std_logic; -- data buffer enable GPIO_CS_N : out std_logic -- data buffer enable
); end system;
architecture structural of system is
component IBUFG port ( O : out std_ulogic; I : in std_ulogic ); end component;
component DCM_INST port ( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLKDV_OUT : out std_logic; CLKIN_IBUFG_OUT : out std_logic; CLK0_OUT : out std_logic; LOCKED_OUT : out std_logic ); end component;
component BUFG port( O : out std_ulogic; I : in std_ulogic ); end component;
-- internal block ram to store read data -- must convert to little endian when plugging in address
component sub_sys is port ( clk : in std_logic; --driven by 100mhz clk A : out std_logic_vector(0 to 31); --A, OE, WE, D are shared flash & sram D : inout std_logic_vector(0 to 31); TRGT_IRQ : in std_logic ); end component;
--------------------------------------------------------------------------------
-- internal signals
-------------------------------------------------------------------------------- signal opb_clk_int : std_logic; signal clk_div_buf : std_logic; signal opb_clk_buf : std_logic; signal dcm_clk0_buf : std_logic; signal locked : std_logic; signal dcm_clk0 : std_logic; signal dcm_clkdv : std_logic;
begin
--------------------------------------------------------------------------------
-- instantiations
--------------------------------------------------------------------------------
sub_system : sub_sys port map ( clk => clk_div_buf, A => A, D => D, TRGT_IRQ => TRGT_IRQ );
buffered_100 : BUFG port map ( I => DCM_CLK0, O => DCM_CLK0_BUF );
buffered_50 : BUFG port map ( I => DCM_CLKDV, O => clk_div_buf --DCM_CLKDV_BUF );
Inst_DCM_INST : DCM_INST port map ( CLKIN_IN => OPB_Clk, RST_IN => SYS_RESET, CLKDV_OUT => DCM_CLKDV, CLKIN_IBUFG_OUT => opb_clk_int, CLK0_OUT => DCM_CLK0, LOCKED_OUT => locked );
SYS_ACE_CS_N