I'm working with avnet v2p dev board trying to communicate with the device via the pci bus right now i want to see if any of the signals i'm sending over the bus is recieved by the device. This means using chipscope.. i think.
I can add a chipscope core to the design and synthesize and generate a bit file, then configure the v2p I monitor the signal TRGT_IRQ to see if the device is seeing it when i write it to the pci BUS. I use an internal DCM to generate a 50 mhz internal clock now when i try to use chipscope to connect and monitor the board the program sits and waits with no response from the jtag chain. (however i can fire up impact and configure various devices via the jtag chain, so i know the jtag cable is functioning) is there some board setting that needs to be changed? do i need to assigned specific I/O pins to the top level design for the jtag chain to work?
thanks for your help.