Hey folks,
OK, I'm feeling a little silly here. I'm trying to use a dual port ram in a xilinx v2p device, and I'm having problems reading data back from the ram. Using modelsim, I can see that my data is getting written to the ram, but I never see the data on the ram's output port during read cycles.
I'm writing data into the ram at one clock rate, and reading at another. The idea is wen goes high, and I fill up the ram with a sequence of data. Then after a few cycles, wen goes low, and the data is read out at a slower rate to eventually get sent to the PPC and out a serial port. Am I mising something in my code? I've included it below, following the language templates in ISE.
module example_ram (wclk, rclk, din, dout, waddr, raddr, wen);
input wclk; input rclk; input wen; input [8:0]waddr; input [8:0]raddr; input [31:0]din;
output [31:0]dout;
// dual port capture ram RAMB16_S36_S36 ram_0 ( .DOA(), // Port A 32-bit Data Output .DOB(dout[31:0]), // Port B 32-bit Data Output .DOPA(), // Port A 4-bit Parity Output .DOPB(), // Port B 4-bit Parity Output .ADDRA(waddr[8:0]), // Port A 9-bit Address Input .ADDRB(raddr[8:0]), // Port B 9-bit Address Input .CLKA(wclk), // Port A Clock .CLKB(rclk), // Port B Clock .DIA(din[31:0]), // Port A 32-bit Data Input .DIB(), // Port B 32-bit Data Input .DIPA(), // Port A 4-bit parity Input .DIPB(), // Port-B 4-bit parity Input .ENA(1'b1), // Port A RAM Enable Input .ENB(1'b1), // PortB RAM Enable Input .SSRA(1'b0), // Port A Synchronous Set/Reset Input .SSRB(1'b0), // Port B Synchronous Set/Reset Input .WEA(wen), // Port A Write Enable Input .WEB(1'b0) // Port B Write Enable Input );
endmodule
Thanks,
-- Matt