Field-Programmable Gate Arrays

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Xilinx ISE 6.3i on Gentoo Linux

Dear all, I'm having some problems installing Xilinx ISE on a Gentoo system. It's the same problem that has plagued man...
4 comments posted 21yrs
posted by ajg112
4 comments posted 21yrs posted by ajg112

Regarding clock muxing

Hi all, I have got two high frequency clocks , i need to select one of them, but while muxing the output clock(one of th...
3 comments posted 21yrs
posted by praveen.kantharajapura
3 comments posted 21yrs posted by praveen.kantharajapura

high speed image capture

hi all, Im in the need of capturing images at about 500 Frames per second and sending all raw data to PC through some p...
8 comments posted 21yrs
posted by manusha
8 comments posted 21yrs posted by manusha

Re: memory in verilog(its urgent plz help)

> hi, > > i made a architecture,in which i want to run 18 proccessing elements > parrallely.Each processing element is...
0 comments posted 21yrs
posted by martin.j.thompson
0 comments posted 21yrs posted by martin.j.thompson

Microblaze

Hey all...i am trying to incorporate a noise generator using FPGA. can easily generate and control noise through Xilinx...
0 comments posted 21yrs
posted by cspatel
0 comments posted 21yrs posted by cspatel

creating HARD MACROs broken in ISE 7.1 SP3 ?

Hi I wonder if Xilinx does any testing of their releases at all - creating Hard Macros seems to be impossible in 7.1 as...
21 comments posted 21yrs
posted by antti
21 comments posted 21yrs posted by antti

use of memory in verilog(uegent please)

hi i made a architecture,in which i want to run 18 proccessin elements parrallely.Each processing element is connect wi...
0 comments posted 21yrs
posted by ravindra28d
0 comments posted 21yrs posted by ravindra28d

[Q] Virtex-IV with RLDRAM-II any experience with it?

For a fast imaging system, we plan to use the LX60 together with x36 organized RLDRAM-II devices? Has someone else allr...
0 comments posted 21yrs
posted by meng.engineering
0 comments posted 21yrs posted by meng.engineering

Clocks

Hello, does anybody know about clock accuracy - I need a very stable clock to synchronize 2 devices via a RF connection...
4 comments posted 21yrs
posted by holzi_stefan
4 comments posted 21yrs posted by holzi_stefan

LatticeXP availability

Hello, Anybody knows when LatticeXP parts will be available over distributors in small quantities? Less than 25 pcs. Tha...
1 comments posted 21yrs
posted by veselic
1 comments posted 21yrs posted by veselic

XILINX POWERPC <-> Embedded tri-mode-MAC connection

Hi, I'm using the Xilinx Platform Studio and I'm tryng to connect the embedded tri-mode-MAC with the PowerPC405. readin...
1 comments posted 21yrs
posted by francesco.poderico
1 comments posted 21yrs posted by francesco.poderico

rom

hi i posted the following already in comp.lang.vhdl but perhaps somebody can help me here: i created a lookup Table: ty...
3 comments posted 21yrs
posted by u_stadler
3 comments posted 21yrs posted by u_stadler

Delays in verilog

Hi, I'm a bit confused by the do's and dont's of delay's (#) in verilog, like the following snippet : always @(posedge c...
7 comments posted 21yrs
posted by gertvierman
7 comments posted 21yrs posted by gertvierman