Regarding clock muxing

Hi all,

I have got two high frequency clocks , i need to select one of them, but while muxing the output clock(one of the two high will be gated).

Is there any way to avoid this.

Regards, Prav

Reply to
praveen.kantharajapura
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I'm not sure what you're asking here. Are you talking about avoiding "runt" clock pulses (switching glitches)? Newer Xilinx components (since Virtex II) have BUFGMUX components which handle this properly.

Without the built-in BUFGMUX, you would need to create a synchronous gating circuit for each input clock that guarantees only one clock is enabled at any time and that each clock gates on or off synchronously. This produces an output clock that has a stretched low (or high depending on active state of gating) period during the switch but never a short low or high period. All this gating will however cause some delay, so the phase relationship to the input clocks may not be good enough for "high speed" clocks.

Reply to
Gabor

Praveen,

BUFGMUX in xilinx devices is built in such way that it ensures synchronous clock muxing.

Vladislav

Reply to
Vladislav Muravin

Click on

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for a simple circuit that lets you switch asynchronously between two clocks. Never any glitches or runt pulses, even when the Select signal is totally asynchronous. Note that both incoming clocks must run continuously, since the circuit cannot switch away from a dead clock.

Peter Alfke, Xilinx

Reply to
Peter Alfke

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