Delays in verilog

Hi,

I'm a bit confused by the do's and dont's of delay's (#) in verilog, like the following snippet :

always @(posedge clk) load_r

Reply to
Gerr
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In this case, 'not synthesisable' means the same thing as ignored - the value of the delay will be set to (nominally) zero for synthesis.

The delay is needed for some simulation purpose, possibly because the block that is being fed by your signal load_r has some hold time requirement with respect to the clock. This is likely to be the case if the downstream block is a simulation model of something that actually requires hold time in real life.

Reply to
allanherriman

Some people like to put the delay in as you've shown so that when they look at wavfeforms in their simulation they clearly see the clock transition, a delay, then the register changes.

The delay is ignored by synthesis tools.

Delays are also useful for modeling input/output delays in testbenches to mimic what happens in I/O buffers.

I hope this helps.

John Providenza

Reply to
johnp

Reply to
Jonathan Bromley

The only purpose of these delays (at least in most OpenCores designs) is to allow a better view of the signals in the waveform viewer. If the signals of a clocked process change at the same time of the clock it could be confusing.

Regards

Javier

Reply to
Javier Castillo

my understanding of verilog is that the code below is umbigous, so it is a bad practice anyway, with or without delays. The reason of the ambiguity is that assignements are analyzed in parallel, so if condition 2 is true, you don't know if the synthezaizer implemented out_reg Consider the following rather useful synthesis idiom:

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Tullio Grassi

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Reply to
Tullio Grassi

Reply to
Jonathan Bromley

I would agree... I do this quite often in VHDL using the same idea.. statements are executed is sequence within a process... processes are executed in parallel. this is a good way to generate strobes which have one on condition and multiple off conditions. I just have a section of "defaults" after the clock. Quite nice in state machines to keep states uncluttered... and it means states only care about the tasks each state knows about (or cares about).

Simon

Reply to
Simon Peacock

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