Field-Programmable Gate Arrays

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EDK and ISE questions

1. When creating a core in EDK 7.1 when it creates the dirver file there is a core_selftest.c file at it includes a ref...
1 comments posted 21yrs
posted by nrivera.eng
1 comments posted 21yrs posted by nrivera.eng

ASIC suggestions

We're about to move an existing design to an ASIC. The prototype was built using a small PIC and some discretes, so the...
9 comments posted 21yrs
posted by david.pariseau
9 comments posted 21yrs posted by david.pariseau

Xilinx: Where has all the data gone?

Browsing the Xilinx website documentation I seem to get no data sheets, user guides, or package drawings. Just: Sorry.....
1 comments posted 21yrs
posted by gabor
1 comments posted 21yrs posted by gabor

XBERT module.

I am a FPGA beginner. So, I worry that my question might be stupid. Can I put a XBERT module on FPGA platform? Does anyo...
2 comments posted 21yrs
posted by sjm1218
2 comments posted 21yrs posted by sjm1218

Using an oscillator in a rugged environment

Dear everybody, I have to design an ALTERA Cyclone FPGA based board which will be used in a rugged environment in terms...
3 comments posted 21yrs
posted by alessandro.strazzero
3 comments posted 21yrs posted by alessandro.strazzero

Cypress CY7B923/33 models

Hi All, I am looking for a VHDL model for the CY7B923 and CY7B933 Hotlink Transmitter and Receiver. The tech support at...
5 comments posted 21yrs
posted by ernielin
5 comments posted 21yrs posted by ernielin

Xilinx Forge compiler is discontinued ??

hi anybody knows where did the download for Forge compiler evaluation disappear at www.xilinx.com ??? there are still f...
1 comments posted 21yrs
posted by antti
1 comments posted 21yrs posted by antti

Rapid prototyping in FPGA

Hi all, Can any one tell me what is RAPID PROTOTYPING and how will this technology help us in faster designing of produ...
3 comments posted 21yrs
posted by sarath1111
3 comments posted 21yrs posted by sarath1111

How to setup Analyzer in ChipScope Pro

Dear Due to lack of experience, I am having a hard time :) to debug the following with ChipScope Pro. My goal is to see...
3 comments posted 21yrs
posted by pasacco
3 comments posted 21yrs posted by pasacco

Welcome back Mr. Knapp

Hi Steven, Since you're back, can you refresh us on Spartan3E availability? Luiz Carlos. P.S. Supposing "Steve Knapp" an...
8 comments posted 21yrs
posted by oen_no_spam
8 comments posted 21yrs posted by oen_no_spam

Fast Recompilation of an XPS project

Hello All: I am new to embedded development and fpgas in general so please bear with me. I am working with EDK 6.3 on a...
2 comments posted 21yrs
posted by suhrid_bhatt
2 comments posted 21yrs posted by suhrid_bhatt

MPEG-2 links please

Hallo all, I am Monica from Germany working on data transmission over DVB.I must implement a MPEG-2 frame generator in...
3 comments posted 21yrs
posted by monica_dsz
3 comments posted 21yrs posted by monica_dsz

Linux driver for Embedded TEMAC in Virtex4

Hello, I am trying to run the embedded TEMAC in the Virtex4 under Linux. A design with the EMAC IP Core from the EDK is...
2 comments posted 21yrs
posted by google_comp.arch.fpga
2 comments posted 21yrs posted by google_comp.arch.fpga

partial reconfig with multipiers

hi there, i am trying to generate a partial bitstream for a module using a multipier. the code is quite simple, just a...
0 comments posted 21yrs
posted by eem
0 comments posted 21yrs posted by eem