does anybody know about clock accuracy - I need a very stable clock to synchronize 2 devices via a RF connection. They must exactly have the same clock, at this time I'm using a 100 MHz clock generator and a Spartan-3 fpga. But for my intended purpose it's not accurate enough. That means, on a scope my generated data bursts of each device with a interval of 3 us are "running away" (that ones those aren't triggered). The 3 us intervals differ perhaps in half a ns or something. Is there a practicable solution for such a problem? Does a DLL with clock mirroring eliminate the problem?

Thanks in advance,


Reply to
Loading thread data ...


DLL with clock mirroring would eliminate a skew between the clocks, but if I understand you correctly, you are facing not a simple issue, especially because you have 100 MHz and you want to use RF connection as a link. That is, you have to embed certain information in the outgoing data, such as the information about your local clock.

The common way to do this is to run, for example, 50-bit wide counter with

100 MHz clock in one end and transfer the value of the counter through the data to another end. In the another end, there is the same counter and this value is compared with the one embedded in the data traffic. The difference between the two gives you an estimation about the difference between the two clocks.

The rest depends on the device that you are using for clock generation and its crystal pullability or frequency range that you can use. If your clock would have been much slower, there is a way to do this using very high-speed clock & phase shift technique.

If you could give a few more details..........

Hope this helps. Vladislav

Reply to
Vladislav Muravin

Hello Vladislav,

the problem is that I cannot transfer data via my RF link. (in the end this is the aim...) I just transmit bursts of a 200 Mbit signal with a interval of 3 us. These bursts contain data for a spread spectrum calculation, and are only used with a analog correlator. To transmit data, I invert the bits from this burst and after that on the correlator the output is -1 (instead of 1 before). And for this purpose, I have to synchronize these 2 bursts. I just tried to use a DCM for clock generation, with no effect. Really annoying... I got so far in this project and now this problem...

Any suggestions?

Regards, Stefan

"Vladislav Muravin" schrieb im Newsbeitrag news:8wJKe.8472$










Reply to

I'm aware this is not an analog forum... Squaring the signal would give 200MHz. You could phaselock your squared oscillator to the incoming stream.


Ing.Buero R.Tschaggelar -
& commercial newsgroups -
Reply to
Rene Tschaggelar


My knowledge of SSC is pretty scarce, but from what I do remember, the problem you are facing is not trivially solvable (I hope I am wrong here) unless can obtain a direct or indirect information about the clock, which you are using as a sampling clock, correct? (and this is the problem!) Because if this is not a sampling clock...

Again, I hope I am wrong.


Reply to
Vladislav Muravin

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.