Latest threads in Field-Programmable Gate Arrays

Different Synthesis Results on Different Levels of Hierarchy (different amount of occupying slices)

Hello, I have some design with regular structure (i.e. resembling 2D array), synthesizing in ISE 6.3 (for Spartan 3).An...

7 21yrs

al.lopich

7 21yrs al.lopich

uDMA Hard drive interface - putting together multiple programs.

I know have a working IDE interface utilizing the PIO transfer mode. I'm only concerned with writing data so it is only...

4 21yrs

Terradestroyer

4 21yrs Terradestroyer

Generic Memory-Mapped VHDL Module

Hello all, I've futzed around with this enough--time to ask the experts! I am working on a design for a Spartan 3 FPGA...

2 21yrs

spam1

2 21yrs spam1

Problem in using Hard Macros in Xilinx ISE 7.1

Hi, I am trying to use hard macros in my design but somehow Xilinx PAR tool goes in an infinite loop during placement w...

0 21yrs

lovesinghal

0 21yrs lovesinghal

How can I see the waveform of my verilog codes?

Regards: I use "Icarus Verilog" as a synthesis and simulation tool.But How can I see the waveform of my verilog codes? t...

1 21yrs

mikelinyoho

1 21yrs mikelinyoho

chipscope pro 6.3i clocking issue

but i have have this problem and think that a small change somewhere will fix it. i have been using xilinx system gener...

1 21yrs

wolf359mmcb

1 21yrs wolf359mmcb

Problem in timing simulation(Altera)

Hi all, The following piece of code works in functional simulation --**************************************************...

1 21yrs

praveen.kantharajapura

1 21yrs praveen.kantharajapura

ISE7.1i SP3, Dual port block ram, coregen issue

Hi, I am using ISE7.1i + SP3 target on a Virtex-4 FX12 fpga. The dual port block ram core generated by Coregen does not...

2 21yrs

zhg.liu

2 21yrs zhg.liu

Spartan slave-parallel development board

Maybe someone can point me in the right direction: I need a Spartan development board (with about an XC3S1500) that sup...

0 21yrs

johannes.vanderhorst

0 21yrs johannes.vanderhorst

Symmetric clocks with ALTERA Quartus

Hi Folks, in my ALTERA based cpld design (no on-chip pll) i need to low-jitter phase lock a frequency of 6.144 Mhz to a...

2 21yrs

df6jb

2 21yrs df6jb

Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;

My mind is boggling. Experimenting with Quartus 5.0 SP1 (targeting an EP1C20F400C7) I was quite puzzled to find that te...

6 21yrs

foobar

6 21yrs foobar

real constants in XST

I'm trying to use some real constants in synthesis. I expect them to be truncated to binary values, but it appears XST...

2 21yrs

arlencox

2 21yrs arlencox

Sharing SDRAM on Stratix II DSP Development kit

I would like to implement a design that shares the external SDRAM that is installed on the Stratix II DSP Development K...

0 21yrs

bjskill

0 21yrs bjskill

Using very large number in VHDL

Hello, I need to use large number (up to 12 774 182 400) in my design, bigger than a typical long. The question is : ho...

6 21yrs

nick

6 21yrs nick

Altera mysupport

Hello... Can somebody tell me what people work behind Altera's mysupport? Trying now since a month to explain them to c...

1 21yrs

me

1 21yrs me

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