Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;

yeah they are the same but the quartus isnt that intelligent to make it out. I believe the bit/part selection confuses the tool.

The two designs are not equivalent; they will create functionally different hardware, hence the performance difference. The designer is getting tripped up by a common Verilog gotcha, using a value "1" when he really meant to set a bit to 1. The problem is this line of test2.v: {index3, value3}

I believe you are right, but last I checked Quartus would give one extra bit for a sum.

If value3 and value2 have the same width,

value3

References:

I believe you are right, but last I checked Quartus would give one extra bit for a sum.

If value3 and value2 have the same width,

value3

Glen,

Please check if you are getting the following message:

Warning (10040): Verilog HDL or VHDL arithmetic warning at : loss of carry in addition or borrow in subtraction

If so, then this is a linting message that points out a potential design mistake. It's a related, but nevertheless distinct issue from simple truncation. If you get the truncation warning, you may be using a much older version of the software that didn't distinguish loss of carry from generic value truncation according to Verilog expression sizing rules. If you want you could mail the qar file for your project to me and can confirm.

Hope this helps, Subroto Datta Altera Corp.

I am not sure of the exact message, but yes, it is getting a warning message like that. The reason I comment on it is because I believe that verilog specifies that it has the correct width. I probably have (had, I am not working on that project currently) an older version of Quartus, so the message may have been different. I believe it actually specifies the width being used. Otherwise, yes, as a lint type warning it is fine.

-- glen