I would like to implement a design that shares the external SDRAM that is installed on the Stratix II DSP Development Kit board between the Nios II controller and custom circuitry that will occupy a portion of the remaining Stratix II LE's (ALM's).
Half of the SDRAM would be dedicated for collecting interleaved 8-bit data samples between the two on-board A/D's. Four of the 8-bit data samples would be accumulated from each A/D and stored, in an interleaved fashion, into a custom-designed FIFO forming a 64-bit word. These 64-bit words would then be written to the SDRAM by either the Nios II processor or a DMA engine @ 12.5 MHz. Once the SDRAM has been filled, the Nios II processor could be notifed (via a register?), where the data samples stored on the SDRAM can be copied and placed into a file in the on-board Compact Flash.
The other half of the SDRAM would be used as the program/data memory for the Nios II processor.
Can the SDRAM be shared by using the Avalon switching fabric to allow the functionality described? Can SOPC Builder be used to ensure that only half of the available on-board SDRAM is used for the Nios II leaving the rest available for storing of the A/D samples?
Any feeback would be would be appreciated.