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Symmetric clocks with ALTERA Quartus

Hi Folks,

in my ALTERA based cpld design (no on-chip pll) i need to low-jitter phase lock a frequency of 6.144 Mhz to a second frequency of 10 MHz. The greatest common divisor of these two numbers is 16000, so i use LPM_COUNTER with modulus 625 to divide the 10 MHz down to 16000 Hz and a modulus 384 LPM_COUNTER to divide the 6.144 MHz to 16000 Hz, everything ok up to this point.

For low-jitter phase comparison usually a xor phase comparator is used. For a xor phase comparator i need the input signals to have an exact 1:1 duty cycle. Since the modulus counters generate only a short (1 clock) impulse when the modulus condition is given, i put a divide-by-two flip-flop behind each counter to produce a 8000 Hz 1:1 duty cycle signal.

While this may work in reality, i get a QUARTUS warning saying that i drive clock inputs with gate outputs. This is clearly true because the modulus output decodes the counter states, but then: What is the "official" way to generate a 1:1 duty cycle signal out of a modulus counter that obeyes the rule that only clocks should feed clock inputs?

TIA for your help Ulrich Bangert

Reply to
Ulrich Bangert
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Use the one cycle wide pulse as a clock enable.

Note that you have serious problem if you are using the output of a state decoder as a clock. It will be full of glitches. You can use it as a clock if you run it through a register. (Costs a cycle of pipeline delay.)

It should work (without the extra register) as a clock enable as long as you can meet setup time.

PS: Be sure to thank the software guys at Altera for saving you from debuging this in the lab.

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Reply to
Hal Murray

Hello Hal,

thank you for your advice.

This is definitely not the case with the modulus output. I am well aware of glitches due to decoding counter states from the times when we used 7490s. The modulus output does not show this behavior, it is clean. That is why i thing that ALTERA did perhaps do a trick or two to avoid the glitches, perhaps enabling the decoded output on a negative clock edge or something like that.

If this were the case (one cycle output from negative to negative edge) this were ok for use as a clock enable signal as you suggest. I will check it.

Best regards Ulrich Bangert

"Hal Murray" schrieb im Newsbeitrag news: snipped-for-privacy@megapath.net...

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Reply to
Ulrich Bangert

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