Hello all,
I've futzed around with this enough--time to ask the experts!
I am working on a design for a Spartan 3 FPGA but that isn't that important. This is the same discussion (I think) for every FPGA family that doesn't have built-in tri-state buffers.
What I am trying to do is to hookup multiple peripheral modules that have all functionality and address decoding contained in separate trees in the hierarchy. The ides is that I can add a uart, digital io, ... peripherals at the top level and none of the logic for the other modules needs to change. All the modules can just hook up to the data bus and the peripheral I/O as need be. All modules would be memory mapped and would connect to the system data bus for uc control.
How I intended to implement this is with a tri-state like bus knowing that the synthesizer would replace the tri-state bus with a mux. That is actually what I want but I'm not sure how to get it.
Below is one such peripheral VHDL module. This is a really simple module but just picture many of these all instantiated on the same bus. Other modules would be things like a UART,...
The problem I am having right now is that XST thinks that there are multiple sources for some of the data bits. There are but I want them all muxed together.
I'd be ecstatic if someone could point me in the right direction.
TIA,
James.
-------------------
entity dig_io is generic ( ADDR_WIDTH : integer := 4; ADDR : std_logic_vector(ADDR_WIDTH-1 downto 0) := "0000"; DATA_WIDTH : integer := 16; IO_WIDTH : integer := 4 ); port ( -- System Control Rst_i : in std_logic;
-- Data Bus nMs_i : in std_logic; nRd_i : in std_logic; nWr_i : in std_logic; Addr_i : in std_logic_vector(ADDR_WIDTH-1 downto 0); Data_io : inout std_logic_vector(DATA_WIDTH-1 downto 0);
-- Peripheral Interface Dig_i : in std_logic_vector(IO_WIDTH-1 downto 0); Dig_o : out std_logic_vector(IO_WIDTH-1 downto 0)
); end dig_io;
architecture Behavioral of dig_io is
signal LOW : std_logic; signal HIGH : std_logic; signal HIZ : std_logic;
signal data_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal data_out : std_logic_vector(DATA_WIDTH-1 downto 0); signal data_oe : std_logic;
signal dig_in_reg : std_logic_vector(IO_WIDTH-1 downto 0); signal dig_out_reg : std_logic_vector(IO_WIDTH-1 downto 0);
begin
---------------------------------------------------------------------------- -- Write from processor to this peripheral
----------------------------------------------------------------------------
data_in LOW);
-- -- Address decoding of write -- process( Rst_i, nWr_i, LOW, HIGH ) begin if( Rst_i = HIGH ) then dig_out_reg LOW); elsif( rising_edge(nWr_i) ) then if( (Addr_i = ADDR) and (nMs_i = LOW) ) then dig_out_reg