Hi, I am trying to use hard macros in my design but somehow Xilinx PAR tool goes in an infinite loop during placement when hard macros are used.
Here are the steps that I did:
- Implemented a standalone multiplier with tight timing constraints on the Virtex 4 sx55 device and with stepping level 2. The "Add IO buffers" option was disabled during synthesis.
- In FPGA editor, a. The extra global signals (of the form XIL_ML_PMV) were trimmed from the multiplier design. b. The remaining design is bounded using "bind" button. (This step does not affect final problem, though) c. The multiplier design is then saved as a hard macro to create an nmc file.
- Wrote a simple Verilog file that used the above created macro name to define a multiplier which is connected to an adder.
- Copied the macro file created in step 2.c to the project directory of second design.
- On implementation of second design, synthesis, translate, and mapping stages run fine. The placer then takes up the full CPU and does not go beyond the following stage even after running for 3-5 hours.
******************* Phase 3.2 (Checksum:1c9c37d) REAL time: 9 secs
Phase 4.30 Phase 4.30 (Checksum:26259fc) REAL time: 9 secs
Phase 5.3 Phase 5.3 (Checksum:2faf07b) REAL time: 10 secs
Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 10 secs
Phase 7.8 ...........
********************The design contains only an adder and multiplier and would otherwise finish in 3-4 minutes.
Am I missing something in the flow or am I doing it wrong?
Thanks in advance, Love Singhal