uDMA Hard drive interface - putting together multiple programs.

I'm not really sure what you mean by "won't simulate"?

There's no reason to use schematics in the design at all (though I'd argue that a top-level schematic can show a design hierarchy very nicely). You can replace your schematic with the equivalent in VHDL to connect your modules together.

Regards, Mark

What I mean by won't simulate is I can't get a waveform back with the Xilinx ISE simulator once I have turned all my vhdl into symbols and wired them in a schematic.

Once I use the create symbol command on the vhdl and then use the symbol in a schematic it doesn't seem to allow me to run a simulation, everything just goes unintialized

This is likely all just because I'm unexperienced with using schematics. Has anyone else had this issue when translatting a vhdl to symbol?

It's easier to "wire" the sub entities into top.vhd with an instance like this:

uart_1: entity work.UART -- using default generic constants port map ( clock => clk_s, -- [in] reset => rst_s, -- [in] address => address_s, -- [in] writeData => writeData_s, -- [in] write_stb => write_stb_s, -- [in] readData => readData_s, -- [out] read_stb => read_stb_s, -- [in] serialIn => serialIn_s, -- [in] serialOut => serialOut_s -- [out] );

Then instance top into your testbench.

-- Mike Treseler

Sounds better than what I've been doing so far.

I'll give it a shot, hopefully it will do the trick and let me see the output waveform.

Thank you

Keith