ISE7.1i SP3, Dual port block ram, coregen issue

Hi, I am using ISE7.1i + SP3 target on a Virtex-4 FX12 fpga. The dual port block ram core generated by Coregen does not contain the initialization data defined in a .ceo file. The simulation using Modelsim is OK after I modified .v file to specify the correct .mif file.

Anyone has same problem and how to solve? Thanks

Reply to
alpha
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Yes, I had that problem. I presume you meant a .coe file. Turns out this is a simulation problem when using that particular core (version

6.2 I believe). In my case, I reverted back to the ver 6.1 core and was able to input a .coe file. After that, simulation worked fine.

Reply to
Marko

Yes version 6.2 core has problem. Not only for Simulation, but also for real implementation. You can modify paremeter c_has_default_data(=0) and c_mem_init_file(=your .mif file name) in generated .v file. This will allow Modelsim work. But still has issue to generate .bit file. I have to switch to single port memory. It works. So I believe it is a tools' bug. Do not know why Xilinx's software has so many problems?

Marko wrote:

Reply to
alpha

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