but i have have this problem and think that a small change somewhere will fix it. i have been using xilinx system generator to design a neural network for FPGA. it seems to synthesize and download properly. i have added a chipscope cores to check if it runs as expected on the FPGA however it complains when run that it has a slow or stopped clock. i interpret this to mean that system generator has not correctly generated the VHDL file or i have missed a step somewhere. please any pointers you have for this problem are appreciated. I am using xilinx system generator, Ise and chipscope Pro version 6.3i with updated ip. the device i am developing for is the virtex 2 pro XCV2p50.
17 years ago