Field-Programmable Gate Arrays

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Should I use DCM for every FPGA design?

I am a newbie in Xilinx FPGA and am trying to prototype my own architecture. I tried the tutorial about stopwatch. Ever...
3 comments posted 21yrs
posted by yijun_lily
3 comments posted 21yrs posted by yijun_lily

Mark to initialize BRAM

Hallo, after I have added a software application project into edk, I can choose the option: "mark to initialize bram"....
0 comments posted 21yrs
posted by marcotoschi
0 comments posted 21yrs posted by marcotoschi

Problem with ModelSim XE

Hello Everyone, I am new to Xilinx and the whole FPGA thing and this might be a very stupid problem that I am facing. A...
7 comments posted 21yrs
posted by learnfpga
7 comments posted 21yrs posted by learnfpga

36x36 signed multiplier?

Multiplier Is there a good algorithm (small) to multiply two 36 bit ?signed? numbers to get a 72 bit result. Is it poss...
4 comments posted 21yrs
posted by blabla
4 comments posted 21yrs posted by blabla

infering a BRAM block for a dual ported ROM

Hi, I have been trying to implementa a 256-deep, 8-bit wide ROM as a BRAM in Xilinx Virtex 4 and Spartan 3(ISE7.1sp2)....
4 comments posted 21yrs
posted by abgoyal
4 comments posted 21yrs posted by abgoyal

SERDES

I'm trying to implement a SERDES interface within a Cyclone device. I've set it up using a PLL, DDIO, a couple of shift...
2 comments posted 21yrs
posted by robnstef
2 comments posted 21yrs posted by robnstef

ISE 7.1 and DCM clkfx

I just upgraded to ISE 7.1.03i. My old 6.3i design used some DCMs in a "not so legal" fashion, where I had CLKFX_DIVIDE...
1 comments posted 21yrs
posted by maplante
1 comments posted 21yrs posted by maplante

Altera NIOS in a Cyclone

Hi: I'm trying to get a NIOS running in an Altera Cyclone FPGA. I'm configuring using a epcs (serial eeprom) then booti...
0 comments posted 21yrs
posted by george.martin
0 comments posted 21yrs posted by george.martin

Phase Offset in Xilinx DDS Core

I'm now using Xilinx DDS Core(v5.0 in ISE7.1i). I wanna generate 2 channels of sine wave, same frequency, different pha...
2 comments posted 21yrs
posted by sutongqi
2 comments posted 21yrs posted by sutongqi

Writing to Spartan 3 SRAM

Hello all, i am very new to FPGA design and struggling to understand how to write data to Spartan 3 SRAM. I am using ve...
3 comments posted 21yrs
posted by amir.intisar
3 comments posted 21yrs posted by amir.intisar

Bootloader Linker Script Help

Hallo, I have compiled "simple bootloader" generated with tool "Program Flash memory" of EDK Platform studio. At Local...
0 comments posted 21yrs
posted by marcotoschi
0 comments posted 21yrs posted by marcotoschi

SystemACE CF and partial reconfiguration

I plan to implement partial reconfiguration by SystemACE CF: 1) produce partial bitstream through the module-based desi...
0 comments posted 21yrs
posted by ghy
0 comments posted 21yrs posted by ghy

Issues with Synplify Pro 7.7 synthesis

Hello All, I am a graduate student in Computer Engineering an am developing some small VHDL modules targeted to Xilinx...
2 comments posted 21yrs
posted by harish.vutukuru
2 comments posted 21yrs posted by harish.vutukuru

DMA issues with IPIF on V2P

Hello, For some reason the DMA drivers generated by the EDK 7.1 for my core write the same word twice when the buffer i...
0 comments posted 21yrs
posted by nrivera.eng
0 comments posted 21yrs posted by nrivera.eng