I have been trying to implementa a 256-deep, 8-bit wide ROM as a BRAM in Xilinx Virtex 4 and Spartan 3(ISE7.1sp2). Prefering to have it inferred instead of instantiating a macro, i wrote it out as a case statement in verilog. ISE correctly infers a block RAM for it.
My problem is i want to do two simultaneous reads from the same ROM (the reads are done on independent clocks). If i implement this as two seperate case statements, even with the exact same data, ISE infers two blockRAMs for them, leaving the second port of each unused.
always @ (posedge clk0) begin case(addr0) 8'h00: data0 = 8'h12; .................... 8'hff: data0 = 8'h34; endcase end
always @ (posedge clk1) begin case(addr1) 8'h00: data1 = 8'h12; .................... 8'hff: data1 = 8'h34; //(exact same data as above) endcase end
Is there a way i can write my verilog so that ISE can infer that i am reading the same ROM, and infer a single, dual-ported RAM block?
I know i can work around it by instantiating a dualport BRAM, i was just wondering if there was a way to have ISE infer it.
Any suggestions appreciated.
Thanks in Advance,