Hi:
I'm trying to get a NIOS running in an Altera Cyclone FPGA. I'm configuring using a epcs (serial eeprom) then booting from FLASH. THe boot process copies a code image from FPASH to SDRAM then jumps to the start in SDRAM.
Running under JTAG is not a problem.
Initially I had RESET* going high before ConfigDone* wnet high. This system would boot OK only if we left power off for 20 seconds or more.
I then linked RESET* to the end of ConfigDone* and this never boots. I also added a delay between RESET* to the NIOS and the NIOS in the fpga. I used the DelayedReset block found in the Cyclone evaluation board design. But that didn't generate any delay. I modified it to work but no different. Never booting.
I've put a logic analyzer on the fpga and see RESET* delayedReset and data being read out of the FLASH.
Has anyone ever got something like this running???
George