I'm trying to implement a SERDES interface within a Cyclone device. I've set it up using a PLL, DDIO, a couple of shift registers, and some output DFF's. I'm seeing some timing issues. How do you compensate for shift (between the data clock and the serial data) that is caused due to the time the PLL takes to lock to the incoming clock?
My PLL is generating 2 clocks: the fast clock to deserialize the data (drives the DDIO and shift registers) and the slower data clock (which drive the output DFF's). In my case I have a 66MHz data clock and a 264MHz deserializer clock.