I'm trying to implement a SERDES interface within a Cyclone device. I've set it up using a PLL, DDIO, a couple of shift registers, and some output DFF's. I'm seeing some timing issues. How do you compensate for shift (between the data clock and the serial data) that is caused due to the time the PLL takes to lock to the incoming clock?

My PLL is generating 2 clocks: the fast clock to deserialize the data (drives the DDIO and shift registers) and the slower data clock (which drive the output DFF's). In my case I have a 66MHz data clock and a 264MHz deserializer clock.

Thank you.

Reply to
Loading thread data ...

Howdy Rob,

Your question doesn't make sense to me. The clock should be running continuously while you want to transfer data, so it only has to lock once (or at least, once in a blue moon). And once it is locked, the PLL generally removes any "shift" (aka propagation delay) associated with using the PLL or global clock network, creating the proper alignment to sample incoming data.

I'm sure Altera has some appnotes on doing stuff like this. Ah, here is but one:

formatting link

Also, what do you mean that you're seeing timing issues? Timing issues, to me, invokes images of having too many levels of logic to fit within a clock period (or in some cases on a V4, any levels of logic :-). That is a completely independent issue from the PLL alignment or locking.

Have fun,


Reply to
Marc Randolph


Thanks for the input. I found the problem. Too many late nights. Sometimes a good nights rest can give you a fresh start.

Take care, rob

Reply to

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.