Hello all,
I am writing a problem that I have designing Standard Cell based designs. I know that this is an FPGA forum, but I am hoping someone here can help me.
I am doing this design flow from Verilog->Netlist->Place&Route. I am doing this for the first time, so as u can imagine I have problems.
According to the documentations I read, I need to generate an edif file, which is a schematic of the design, which is needed for the Floorplanner and then the Place and Route tools.
I am using Synopsys Design Vision, and I am using the right target and symbol libraries, and the file gets compiled alright and I can see the schematic of my design. Now obviously, I should be able to capture this schematic in some sort of a text file (which is edif). But when I try to save as edif, it says that there is no schematic for the current design. There is no documentation at all for this, so I cannot figure out what to do.
If anyone knows about this please let me know. If there is any other way that I can proceed to the Physical design tools also, please do let me know.
Sincerely, Anup