Field-Programmable Gate Arrays

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Altera ByteBlaster II vs ByteBlaster MV

Hi group, I have been using one ByteBlasterMV for a long time now, to program a chain of 4 components in JTAG: EPM12701...
1 comments posted 21yrs
posted by abeaujean
1 comments posted 21yrs posted by abeaujean

Microblaze Simple Bootloader

Hallo, I have made a small microcontroller based on microblaze, I have added the microblaze debug module core. I have c...
0 comments posted 21yrs
posted by marcotoschi
0 comments posted 21yrs posted by marcotoschi

TTL, CMOS and spartan

im looking for some advice/information on how to interface spartan3 FPGA with TTL and CMOS chips. does anybody know any...
5 comments posted 21yrs
posted by manusha
5 comments posted 21yrs posted by manusha

ADC Clock on Stratix II DSP Dev Board

Hello, I recentally purchased a Stratix II (60) DSP Dev Board (from Altera) and I have been having a bit of trouble get...
1 comments posted 21yrs
posted by psolomon
1 comments posted 21yrs posted by psolomon

Single PPC with DES on V2P

Hey to all, Background information: I am doing a project which has a single ppc and a specialize DES core in a Virtex 2...
4 comments posted 21yrs
posted by nrivera.eng
4 comments posted 21yrs posted by nrivera.eng

Single PPC on Virtex 2 Pro DMA problems

Hey to all, Background information: I am doing a project which has a single ppc and a specialize DES core in a Virtex 2...
2 comments posted 21yrs
posted by nrivera.eng
2 comments posted 21yrs posted by nrivera.eng

Help coding a bigger project

I?m wondering what sort of approach I should have in coding a bigger-than-one-entity-system. The system is going to use...
5 comments posted 21yrs
posted by blabla
5 comments posted 21yrs posted by blabla

Drive startup mode - PIO write problems from FPGA

I'm working on an fpga program to write to hard drives and so far I've been pretty successful with the exception of a d...
4 comments posted 21yrs
posted by Terradestroyer
4 comments posted 21yrs posted by Terradestroyer

fpga_editor and fvwm

Hi, i'm trying to start Xilinx fpga_editor on my Debian/Sarge machine. It shows the program window for some millisecond...
0 comments posted 21yrs
posted by fmadlener
0 comments posted 21yrs posted by fmadlener

Spartan and Flash PROM : Boundary Scan

Hello, I am working with a spartan 2 and a PROM XCF01S. Impact software does not recognized the chain of this two compo...
1 comments posted 21yrs
posted by pierre.lefaix
1 comments posted 21yrs posted by pierre.lefaix

Send IP packets at the Ethernet level with VIRTEX4

Hello, I would to use a simple/easy way to send, in multicast address, some IP packets fprm a FPGA Xilinx VIRTEX4 to a...
2 comments posted 21yrs
posted by philippe.hostiou
2 comments posted 21yrs posted by philippe.hostiou

Strange FPGA problem

Hello Guys, I am working on some verfication of the SoC IP. To verify these IP we are implementing it on FPGA. I am fac...
1 comments posted 21yrs
posted by stud_lang_jap
1 comments posted 21yrs posted by stud_lang_jap