Field-Programmable Gate Arrays

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opb ip master/slave...arbiter problems

Hello all, I want to create an IP master on the OPB. I am using Xilinx Virtex2 (xc2v2000), and Xilinx platform studio (...
1 comments posted 21yrs
posted by melbadri
1 comments posted 21yrs posted by melbadri

Altera Programming Cables and EPCS16/64

Hi, I am trying to decide which Altera programming cable to purchase. Can anyone tell me how long it takes them to prog...
0 comments posted 21yrs
posted by hawaiianengineer
0 comments posted 21yrs posted by hawaiianengineer

JBits query

I have installed the JBITS 3.0 SDK from Xilinx. How do I know that the bit pattern has actually changed before download...
1 comments posted 21yrs
posted by sarnaths
1 comments posted 21yrs posted by sarnaths

Xilinx Webpack Schematic

Hi, I am trying to implement a schematic design. My problem is that when I try to assign a constant binary number to on...
2 comments posted 21yrs
posted by jtrabal
2 comments posted 21yrs posted by jtrabal

data logging via JTAG?

Hi. I have a simple board with an Spartan 3 FPGA and a AD connected to it. The board is configured via JTAG using the X...
2 comments posted 21yrs
posted by janbeck
2 comments posted 21yrs posted by janbeck

Xilinx Spartan-3

Hello! I have an application with a Spartan-3 mainboard and 3 spartan-3-based daughterboards -- we had planned on conne...
11 comments posted 21yrs
posted by acetylcholinerd
11 comments posted 21yrs posted by acetylcholinerd

Xilinx ModelSim VHDL Running Two Models

Hello group, How does one combine two models? Specifically, I have a Spartan3 with some models that I have made and con...
8 comments posted 21yrs
posted by bradsmallridge
8 comments posted 21yrs posted by bradsmallridge

Cyclone and NIOS II

Is any using a Cyclone FPGA and NIOS II CPU? Specifically I'm having trouble booting from FLASH. THe boot sequence it t...
0 comments posted 21yrs
posted by gfm5050
0 comments posted 21yrs posted by gfm5050

Output register instantiation in Quartus

Hi, I have been using the following component for Lattice devices when I want a signal to be routet into a fast output...
8 comments posted 21yrs
posted by ALuPin
8 comments posted 21yrs posted by ALuPin

Count "1" bit in bit stream

Hi, all. I'm using Xilinx FPGA with VHDL language. Now I try to build a system, and that system needs a counter which c...
9 comments posted 21yrs
posted by magnacum
9 comments posted 21yrs posted by magnacum

digilent USB2 module

hi all, anyone know how to use digilent USB2 module in B1 connector of the spartan3 starter kit? CMOS
3 comments posted 21yrs
posted by manusha
3 comments posted 21yrs posted by manusha

Xilinx ISE Passing IO pad attributes using UCF file.

Hi, I am using a ucf file to pass pin location, iostandard, slew rate and drive strength constraints to the xilinx PAR...
2 comments posted 21yrs
posted by andrew.newsgroup
2 comments posted 21yrs posted by andrew.newsgroup

JTAG USB Circuit

anyboydy knows how to find the circuit or schematic fo make an JTA USB cable
5 comments posted 21yrs
posted by fecs
5 comments posted 21yrs posted by fecs

EDK libgen cc choice

I'm trying to use an alternative compiler for EDK's libgen (one that supports my special FPU). So far all the options t...
0 comments posted 21yrs
posted by Hua.Zheng
0 comments posted 21yrs posted by Hua.Zheng