Field-Programmable Gate Arrays

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Core import into ISE

I'm trying to implement a project in ISE which comprises some logic and an Aurora core. I generate the Aurora core OK u...
4 comments posted 20yrs
posted by enquiries
4 comments posted 20yrs posted by enquiries

picoblaze IDE for Linux

I've created an IDE for the picoblaze-3 microcontroller (Xilinx TM). The IDE is an open-source project (GPL-license) an...
5 comments posted 20yrs
posted by m6
5 comments posted 20yrs posted by m6

SoC embedded FPGA

I saw an interesting STmicroelectonics' chip which embed an ARM9 core and a FPGA, this is the STW21000. Did someone hea...
5 comments posted 20yrs
posted by gbirot
5 comments posted 20yrs posted by gbirot

ISE 7.1i & Linux / reg code question

Well, John McCluskey and Kamal were right -- the reg code I had was for Foundation with ISIM. A new code for Foundation...
1 comments posted 20yrs
posted by r_fpga_dev
1 comments posted 20yrs posted by r_fpga_dev

problem with Thold violation under quartus

Hi, I've a problem on fitting my vhdl design in a cyclone. The compiler report says "Required P2P time" is longer than...
3 comments posted 20yrs
posted by pinkotronic
3 comments posted 20yrs posted by pinkotronic

program prom by the fpga

Hi, I am trying to program the configuration prom (xcf16p) through dedicated pins of my fpga. i.e I connect some GPIO o...
0 comments posted 20yrs
posted by nahum_barnea
0 comments posted 20yrs posted by nahum_barnea

xilinx ML310 board PCI DMA problem

Hi! all! I have a problem with runing PCI DMA example provided by Xilinx EDK install CD on ML310 board. The file xpci_e...
1 comments posted 20yrs
posted by laoshan.zb
1 comments posted 20yrs posted by laoshan.zb

Simulation : EDK

hi,, I am trying to generate simulation for a edk project. I download the newest MXE files from the xilinx.com and ran...
1 comments posted 20yrs
posted by cybershakith
1 comments posted 20yrs posted by cybershakith

Reprogramming FPGA over PCI???

Hello, I am working on a new project with a Xilinx FPGA (Virtex 2 or Virtex 4...TBD) on a PCI card (actually, a PCI Mez...
9 comments posted 20yrs
posted by john.orlando
9 comments posted 20yrs posted by john.orlando

ISE 7.1i incremental synthesis

I'm trying to get incremental synthesis working with the Xilinx tools, ISE 7.1i. I applied the most recent service pack...
2 comments posted 20yrs
posted by bkuschak
2 comments posted 20yrs posted by bkuschak

Unknown price difference for xilinx fpga

I have been learning about fpga's for a month now, and stumbled across the merec web site. I am looking for a dev board...
2 comments posted 20yrs
posted by coreyhahn
2 comments posted 20yrs posted by coreyhahn

Two short-term research grants

Sorry for cross-posting, but I think that this announcement can be of interest to many readers. SmartLab Dept. of Bioph...
0 comments posted 20yrs
posted by anguita
0 comments posted 20yrs posted by anguita

FPGA's in bulk and pricing

I was wondering where you can obtain 12Q240C8 parts in small quantities.. but no singles... ie: 10-25, in North America...
3 comments posted 20yrs
posted by jai.dhar
3 comments posted 20yrs posted by jai.dhar

Reverse Engineering Output Files

We have an MCS_86 output file for an Xilinx 4000 series device. However, all the design files are missing and we need t...
1 comments posted 20yrs
posted by ian.mcneil
1 comments posted 20yrs posted by ian.mcneil

Testbench failures for Opencores Ethernet mac

Hello, I'm fairly new to this - just got started running the testbench for the Opencores Ethernet core. I'm using Model...
0 comments posted 20yrs
posted by pei
0 comments posted 20yrs posted by pei