Hello! I have an application with a Spartan-3 mainboard and 3 spartan-3-based daughterboards -- we had planned on connecting the daughterboards to the mainboard via SATA connectors, and running a 300 Mbps LVDS link in each direction (M->D and D->M). We had hoped that the daughterboards could do clock-recovery of the incoming (M->D) 300 Mbps stream, and then (since effectively the whole system would be synchronous) this would eliminate the need for explicit clock-recovery on the mainboard (which would be receiving the 3 LVDS streams from the daughterboard.
However, Xilinx engineers told me yesterday that the Spartan-3s have no built-in CDR hardware (which is required to make XAPP250 "work"). So:
- Can anyone recommend any external chips to do this sort of CDR? I've seen clock and data retiming chips available from Maxim, etc. but they all look targeted at optical applications.
- If we run the M->D link at 75 Mbps, recover that clock, use it to drive the daughterboard FPGA, and then (using a DCM) clock-quadruple it to 300 MHz (and use that to send out the 8b/10b data on the D->M differential pair) can I assume that the phase relationship between the D and the M FPGA will be constant (assuming the master FPGA is also running a 4x clock)?
I'll happily take any other suggestions -- I wish I could just feed the8b/10b stream into the DCM, but I guess life isn't that simple :)